AU5325去抖時鐘
  • 輸出頻率范圍:
    up to 2.1GHz
  • 相位噪聲:
    <150fs rms jitter
  • 輸入/輸出:
    4 inputs / 10 outputs
  • 封裝類型:
    64-QFN
AU5325
Features

? Quad PLL frequency translation from 1 of 4 inputs

? DPLL Programmable Bandwidth 1mHz- 4KHz

? Digitally Controlled Oscillator (DCO) Mode Frequency Step Resolution: 0.005 ppb

? Hitless input clock switching: Auto or manual, Maximum phase hit of only 50 ps

? ZDM supported with external feedback connection


System Benefits

? Lower phase noise minimizes bit error rate in the system

? Better signal integrity increases design margin and leads to faster time to market

? Higher clock tree integration reduces system BOM and increases overall reliability

Applications

? OTN/PTN

? BBU/RRU

? LAN Switch/Router with SyncE support

? Small Cell

? Acceleration card

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