• 輸出頻率范圍:
    0.5 Hz-2.94912 GHz
  • 相位噪聲:
    <85fs rms jitter
  • 輸入/輸出:
    4 inputs / 12 outputs
  • 封裝類型:

? Quad PLL frequency translation from any of 4 inputs

? DPLL Programmable Bandwidth 0.09mHz- 4KHz

? Digitally Controlled Oscillator (DCO) Mode: Frequency step resolution 0.001 ppt, Phase adjustment accuracy < 1ps

? Hitless input clock switching: Auto or manual, Maximum phase hit of only 25 ps

? Internal ZDB Mode with <0.5 ns Input-to-Output delay variation

System Benefits

? Lower phase noise minimizes bit error rate and increases design margin in Nx 56G/112G PAM4 I/O systems

? Better signal integrity increases design margin and leads to faster time to market

? Higher clock tree integration reduces system BOM and increases overall reliability


? JESD204B/C Support for data converter clocks



? 100/200/400G/800G Switch/Router with SyncE support

? Small Cell

? Acceleration card

Welcome to contact us for more product information.
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