AU5061時鐘發生器
  • 輸出頻率范圍 :
    0.5 Hz-2.94912 GHz
  • 相位噪聲 :
    <85fs rms jitter
  • 輸入/輸出 :
    4 inputs / 12 outputs
  • 封裝類型 :
    64-QFN
AU5061
Features

? Any frequency clock generation from crystal input or any of 4 input reference clocks

? Programmabled outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude

? Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V

? Digitally Controlled Oscillator (DCO) Mode: Frequency step resolution 0.001 ppt, for frequency margining applications

? Internal ZDB Mode with <0.5 ns Input-to-Output delay variation

System Benefits

? Lower phase noise minimizes bit error rate and increases design margin in Nx 56G/112G PAM4 I/O systems

? Better signal integrity increases design margin and leads to faster time to market

? Higher clock tree integration reduces system BOM and increases overall reliability



Applications

? OTN/PTN

? BBU/RRU

? 100/200/400G/800G Switch/Router with SyncE support

? Small Cell

? Acceleration card

Welcome to contact us for more product information.
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